Flash memory devices are comprised of an array of memory cells, each memory cell being intersected by a word line, sometimes referred to as a row line, and a bit line, sometimes referred to as a column line. Each memory cell may be comprised of a MOS transistor with a control gate and a floating gate. Before a memory cell is programmed, no excess charge exists on the gate of the transistor. As a result, the turn-on voltage of the transistor, V.sub.T is low, and the memory cell may be arbitrarily considered a logical 1. Once the memory cell is programmed by the application of a high voltage to the drain and gate of the transistor, a stored charge accumulates on the floating gate of the transistor, raising the turn-on voltage of the transistor. A programmed memory cell may be arbitrarily considered a logical 0. Erasing or deprogramming a programmed cell involves grounding or applying a negative potential to the control gate and applying an operating voltage to the source of the transistor.
As part of an erase step, each word line in the flash memory device must be preconditioned. Preconditioning is necessary to assure that the turn-on voltage of each cell is uniformly high. During the preconditioning step, the turn-on voltage of each cell is raised so that each cell has roughly the same turn-on voltage.
Because of manufacturing defects a number of word lines of the memory array will be defective. The memory cells in defective rows may have turn-on voltages that are at or below zero. These defective rows and columns can be mapped out of the array of memory cells by replacing the defective rows or columns with redundant rows or columns. Even though defective word lines are mapped out of the memory array, the defective word lines will still physically intersect with good (nondefective) bit lines. The intersection of a defective word line and a good bit line may interfere with a READ operation of nondefective memory cells on the bit line. For example, during a READ operation, if the target cell is a logical 0, i.e., having a high turn-on voltage, and if the defective cell on the bit line has a turn-on voltage at or below zero volts, the sense amplifier will sense the sinking of current by the defective cell. The sense amplifier will then output a logical 1 rather than a logical 0.
As part of the preconditioning step, a conventional strategy for avoiding interference by memory cells in defective rows involves setting the turn-on voltage of memory cells on the defective rows to a high level, thereby preventing these cells from being turned on and sinking current during operation of the flash memory device. To accomplish this, a high voltage, typically 12 volts or more, is applied to the word line and a second voltage, typically 6 volts, is applied to the bit line. The array voltage source, which may be connected to the source of each transistor, is grounded. The remaining word lines are shorted to ground. As a result, the memory cells on the defective row are programmed, resulting in a high turn-on voltage for each transistor in the defective row.
One type of defect occurs when adjacent word lines are shorted together. When adjacent word lines are shorted together, the high voltage applied to the defective word line during preconditioning will be pulled to ground by the ground path through the adjacent shorted defective word line.
In some cases, word lines are shorted across a word line boundary, indicating that a word line in a grouping of eight word lines is shorted to an adjacent word line in a grouping of eight word lines. In this scenario, when a high voltage is applied to a defective word line, the applied voltage may find a path to ground through a shorted word line that is across a word line boundary separating groupings of eight word lines.